1. Field of the Disclosure
The present invention generally relates to a method for fabricating a semiconductor device, and more particularly, to a non-volatile memory device with asymmetric source/drain junctions and a method for fabricating the same.
2. Brief Description of Related Technology
Non-volatile memory devices are mainly used in electronic components that require data retention even when no power is supplied. A non-volatile memory device typically includes a floating gate structure in which a polysilicon film is capped with an inter-poly oxide (IPO). Because non-volatile memory devices are very highly integrated, new cell structures have replaced floating gates.
One of the new cell structures has a charge trapping layer, e.g., a silicon-oxide-nitride-oxide-silicon (SONOS) structure. SONOS devices have excellent reliability in interface or data retention because the nitride film is used as a charge trap site. A SONOS device is a stacked structure on a semiconductor substrate with a channel region, a tunneling layer, a charge trapping layer, a blocking layer, and a control gate electrode.
However, as the integration density of semiconductor devices is increased and design rule is drastically reduced, there are various difficulties in achieving reliable operations of a device. For example, as the width of a gate is reduced, the length of the channel is drastically decreased. Therefore, short channel effect may frequently occur, causing the reduction of the threshold voltage, the increase of leakage current, and the deterioration of the refresh characteristic. Short channel effect may cause punch-through between the source and drain of a transistor. Moreover, punch-through may cause device malfunction.
Because short channel effect frequently occurs in non-volatile memory devices, the reliability of the devices decreases. Short channel effect reduces the threshold voltage of a memory cell, thereby degrading the threshold voltage distribution.